 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PROGRAMMABLE DELAY CHIP ClockWorksTM SY10E195 SY100E195 FEATURES s Up to 2ns delay range s Extended 100E VEE range of -4.2V to -5.5V s s s s s s DESCRIPTION The SY10/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. Because the delay programmability of the E195 is achieved by purely differential ECL gate delays, the device will operate at frequencies of >1GHz, while maintaining over 600mV of output swing. The E195 thus offers very fine resolution, at very high frequencies, selectable entirely from a digital input, allowing for very accurate system clock timing. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. 20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry 75Kk input pulldown resistor Fully compatible with Motorola MC10E/100E195 Available in 28-pin PLCC package PIN CONFIGURATION D7 NC D2 D3 D4 D5 D6 25 24 23 22 21 20 19 D1 D0 LEN VEE IN IN VBB 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 TOP VIEW PLCC J28-1 16 15 14 13 12 NC NC VCC VCCO Q Q VCCO EN SET MIN SET MAX CASCADE NC NC CASCADE PIN NAMES Pin IN/IN EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Minimum Delay Set Maximum Delay Set Cascade Signal Rev.: E Amendment: /0 1 Issue Date: October, 1998 ClockWorksTM SY10E195 SY100E195 VBB IN 1 0 1 1 1 1 1 *1.5 Q LEN Latch D 7-Bit Latch 1 1 1 0 0 0 IN EN *1.25 LEN SET MIN SET MAX 4 gates 0 1 8 gates 0 1 16 gates 0 1 1 1 Q Cascade CASCADE CASCADE D0 D1 D2 D3 D4 D5 D6 D7 *Delays are 25% or 50% longer than standard (standard = 80ps). Micrel BLOCK DIAGRAM 2 0 Q Micrel ClockWorksTM SY10E195 SY100E195 DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 130 130 156 156 -- -- 130 130 156 156 -- -- 130 150 156 179 Min. -- Typ. -- Max. 150 Min. -- TA = +25C Typ. -- Max. 150 -- TA = +85C Min. Typ. -- Max. 150 Unit A mA Condition -- -- 3 Micrel ClockWorksTM SY10E195 SY100E195 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output IN to Q; Tap = 0 IN to Q; Tap = 127 EN to Q; Tap = 0 D7 to CASCADE Programmable Range tPD (max.) - tPD (min.) Step Delay D0 High D1 High D2 High D3 High D4 High D5 High D6 High Linearity Duty Cycle Skew, tPHL-tPLH Set-up Time D to LEN D to IN EN to IN Hold Time LEN to D IN to EN Release Time EN to IN SET MAX to LEN SET MIN to LEN Jitter Rise/Fall Times 20-80% (Q) 20-80% (CASCADE) Min. 1210 3320 1250 300 2000 Typ. 1360 3570 1450 450 2175 Max. 1510 3820 1650 700 -- TA = +25C Min. 1240 3380 1275 300 2050 Typ. 1390 3630 1475 450 2240 Max. 1540 3880 1675 700 -- TA = +85C Min. 1440 3920 1350 300 2375 Typ. 1590 4270 1650 450 2580 Max. Unit ps 1765 4720 1950 700 -- ps ps -- -- 55 115 250 505 1000 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 17 34 68 136 272 544 1088 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 105 180 325 620 1190 -- -- -- -- -- -- -- -- -- -- -- 325 650 -- -- 55 115 250 515 1030 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 17.5 35 70 140 280 560 1120 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 105 180 325 620 1220 -- -- -- -- -- -- -- -- -- -- -- 325 650 -- -- 65 140 305 620 1240 D1 -- 200 800 200 500 0 300 800 800 -- 125 300 21 42 84 168 336 672 1344 D0 30 0 -- -- 250 -- -- -- -- <5 225 450 -- -- 120 205 380 740 1450 -- -- -- -- -- ps -- -- ps -- -- -- -- 325 650 ps ps 5 4 -- ps ps 2 3 7 1 -- 6 Condition -- tRANGE t Lin tskew tS tH tR tjit tr tf 8 -- NOTES: 2. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 3. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set. 4. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75mV to that IN/IN transition. 5. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75mV to that IN/IN transition. 6. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 7. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 8. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). Typically, the device will be monotonic to the D0 input, however, under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB, the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 9. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques. 4 Micrel ClockWorksTM SY10E195 SY100E195 APPLICATIONS INFORMATION ADDRESS BUS (A0 - A6) A7 D6 D2 D4 D5 D3 D4 D7 D2 D1 D0 LEN VEE Input IN E196 Chip #1 VCC VCCO Q Q VCCO D3 D1 D0 LEN VEE IN E196 Chip #2 VCC VCCO Q Output Q VCCO CASCADE CASCADE VBB VBB Figure 1. Cascading Interconnect Architecture Cascading Multiple E195s To increase the programmable range of the E195, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple E195s without the need for any external gating. Furthermore, this capability requires only one more address line per added E195. Obviously, cascading multiple PDCs will result in a larger programmable range; however, this increase is at the expense of a longer minimum delay. Figure 1 illustrates the interconnect scheme for cascading two E195s. As can be seen, this scheme can easily be expanded for larger E195 chains. The D7 input of the E195 is the cascade control pin. With the interconnect scheme of Figure 1, when D7 is asserted, it signals the need for a larger programmable range than is achievable with a single device. An expansion of the latch section of the block diagram is pictured below. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D7 of chip #1 above is low, the cascade output will also be low, while the cascade bar output will be a logical high. In this condition, the SET MIN pin of chip #2 will be asserted and, thus, all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Since the RESET and SET inputs of the latches are overriding, any changes on the A0-A6 address bus will not affect the operation of chip #2. Chip #1, on the other hand, will have both SET MIN and SET MAX de-asserted so that its delay will be controlled entirely by the address bus A0-A6. If the delay needed is greater than can be achieved with 31.75 gate delays (1111111 on the A0-A6 address bus), D7 will be asserted to signal the need to cascade the delay to the next E195 device. When D7 is asserted, the SET MIN pin of chip #2 will be de-asserted and the delay will be controlled by the A0-A6 address bus. Chip #1, on the other hand, will have its SET MAX pin asserted, resulting in the device delay to be independent of the A0-A6 address bus. When the SET MAX pin of chip #1 is asserted, the D0 and D1 latches will be reset while the rest of the latches will be set. In addition, to maintain monotonicity, an additional gate delay is selected in the cascade circuitry. As a result, when D7 of chip #1 is asserted, the delay increases from 31.75 gates to 32 gates. A 32-gate delay is the maximum delay setting for the E195. To expand this cascading scheme to more devices, one simply needs to connect the D7 input and CASCADE outputs of the current most significant E195 to the new most significant E195 in the same manner as pictured in Figure 1. The only addition to the logic is the increase of one line to the address bus for cascade control of the second PDC. 5 CASCADE SET MIN EN SET MAX EN SET MIN CASCADE IN IN SET MAX D5 D6 D7 Micrel SET MAX SET MIN LEN LEN LEN LEN LEN LEN LEN LEN D0 Reset Reset Reset Reset Set Reset Set Reset Set Reset Set Reset Set Reset Bit 0 Q0 D1 Bit 1 Q1 D2 Bit 2 Q2 D3 Bit 3 Q3 D4 Bit 4 Q4 D5 Bit 5 Q5 D6 Bit 6 Q6 D7 Bit 7 Q7 To Select Multiplexers ClockWorksTM SY10E195 SY100E195 PRODUCT ORDERING CODE Ordering Code SY10E195JC SY10E195JCTR SY100E195JC SY100E195JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Figure 2. Expansion of the Latch Section of the E195 Block Diagram CASCADE CASCADE 6 Micrel ClockWorksTM SY10E195 SY100E195 28 LEAD PLCC (J28-1) Rev. 03 7 Micrel ClockWorksTM SY10E195 SY100E195 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 8 |
Price & Availability of SY10E195
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |